1. Field of the Invention
The subject matter disclosed herein relates to the field of fabrication of microstructures, and, more particularly, to a test structure for process qualification of a metallization process in integrated circuit manufacturing.
2. Description of the Related Art
In microstructures such as integrated circuits, a large number of circuit elements, such as transistors, capacitors and resistors, are fabricated on a single substrate by depositing semiconductive, conductive and insulating material layers and patterning those layers by photolithography and etch techniques. In subsequent manufacturing steps, the individual circuit elements may be electrically connected by means of metal lines that are embedded in a dielectric, thereby forming what is usually referred to as a metallization layer. In modern integrated circuits, a plurality of such metallization layers is typically provided, wherein the layers are stacked on top of each other to obtain the required functionality. Failure of these metal lines may lead to a failure of part or the whole semiconductor device. Therefore, the reliability and quality of the metal lines is of particular interest and is even more important for highly integrated circuit devices having reduced dimensions of the circuit elements as well as of the metal lines.
In general, subsequent material layers should exhibit good adhesion to each other while at the same time maintaining the integrity of each individual layer, i.e., chemical reaction of adjacent layers and/or diffusion of atoms from one layer into the other layer should be avoided during the manufacturing processes for the fabrication of the individual layers and subsequent processes as well as afterwards when operating the completed device. To meet these requirements, often an intermediate layer is required to provide good adhesion and to suppress diffusion and thus undue interference between neighboring materials during processing and operation. A typical example for such requirements in the fabrication of semiconductor devices is the formation of interconnect plugs, wherein openings having a bottom region and a sidewall region have to be provided with a corresponding intermediate layer, that is, a conductive barrier layer, so that a subsequently deposited conductive material exhibits good adhesion to the surrounding dielectric layer and undue interaction during processing and operation may be avoided. The same requirements should be met for the metallization layers to which the interconnect plugs are connected. In advanced semiconductor devices, the interconnect plugs are typically formed of a tungsten-based material and provided in an interlayer dielectric stack which is typically comprised of silicon dioxide including a bottom etch stop layer typically formed of silicon nitride. In other semiconductor devices, the interconnect plugs may be formed of a copper-based material. Depending on the material used for the plugs, an appropriate barrier material has to be chosen, examples of which are well known in the art. For example, for a tungsten-based material plug, a barrier layer of titanium/titanium nitride may be used, whereas for a copper-based material plug, a barrier layer comprising tantalum and/or tantalum nitride may be used. In modern integrated circuits, openings (so-called vias) are formed exhibiting an aspect ratio that may be as high as approximately 8:1 or more, and the opening may have a diameter of 0.1 μm or smaller. The aspect ratio of such openings is generally defined as the ratio of the depth of the opening to the width of the opening.
The metal lines of the metallization layers may be formed of the same materials as the interconnect plugs. For example, the contact holes (vias) as well as trenches for the metal lines may be etched and subsequently filled by the same deposition process of the conductive material(s), which is usually referred to as a double damascene process. In other semiconductor devices, the metal lines are formed separate from the interconnect plugs. Typical materials for the metal lines are copper-based materials or aluminum-based materials.
In order to facilitate the testing of the metallization structures including the metal lines of the metallization layers as well as the interconnect plugs, test structures are typically provided which are formed on the same wafer as the integrated circuit and which are formed by the same processes used for the fabrication of the semiconductor devices on the wafer. Typically, these test structures are provided for mechanical integrity tests as well as electromigration or stress-induced voiding tests and typically employ open-ended chains of alternating metal levels. The testing of such test structures is generally limited by the number of available bond pads that may be connected to points on the test structure.
One point of interest may be electromigration in the test structure. Electromigration is the migration of metal atoms in a conductor due to electrical current. Material transport due to electromigration may give rise to voids and hillocks which can cause open or short circuit failure. Generally, electromigration depends on the current density as well as on the geometry of the respective conductors. For example, a higher current density increases the material transport due to electromigration. Further, there exists a certain length of conductor known as Blech length, below which electromigration does not occur because the material transporting forces due to the electrical current are at least partially compensated by a developing mechanical stress.
A further point of interest is stress migration, i.e., a material transport in a conductor due to a mechanical stress. Such a mechanical stress may arise due to a change in temperature wherein the different thermal extension of the conductive materials and the surrounding dielectric generate a large mechanical stress. For testing stress migration failure, the test structure may be heated to a temperature in a range from, e.g., about 150-350° C. Usually the testing temperature is higher than the temperature of the semiconductor device during operation in order to achieve a stress migration result in reasonable time. In order to heat the test structure, it may be placed within a heating chamber and a resistance meter may be coupled to the test structure for measuring resistance across the test structure such that the formation of a void within the test structure due to stress migration causes an increase in the resistance measured by the resistance meter. In other testing environments, the time to stress migration failure of a test structure is reduced by continuously conducting a certain electrical current through the test structure that is continuously heated.
Both electromigration and stress migration are mechanisms that degrade the reliability of the semiconductor device and are therefore important parameters for the design of semiconductor devices.
Current stress migration structures are represented in numerous different structures and require a large number of electrical probe pads and usually do not allow for one hundred percent physical failure analysis.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.